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What is ‘instruction scheduling’?
A. A technique for reordering instructions to minimize pipeline stalls and improve performance
B. A method for managing memory access
C. A process for optimizing CPU performance
D. A technique for handling data hazards
Answer: A technique for reordering instructions to minimize pipeline stalls and improve performance
What is ‘static branch prediction’?
A. A technique that uses a fixed strategy to predict branch outcomes, regardless of execution history
B. A method for managing memory access
C. A process for optimizing CPU performance
D. A technique for handling data hazards
Answer: A technique that uses a fixed strategy to predict branch outcomes, regardless of execution history
What is ‘dynamic branch prediction’?
A. A technique that adjusts predictions based on the actual execution history of branch instructions
B. A method for managing memory access
C. A process for optimizing CPU performance
D. A technique for handling instruction pipelines
Answer: A technique that adjusts predictions based on the actual execution history of branch instructions
What is ‘instruction-level parallelism’?
A. A measure of how many instructions can be executed simultaneously
B. A process for managing memory access
C. A technique for optimizing CPU performance
D. A method for handling data hazards
Answer: A measure of how many instructions can be executed simultaneously
What is ‘instruction throughput’?
A. The number of instructions a CPU can execute in a given time period
B. The speed of the CPU clock
C. The amount of data that can be transferred over the bus
D. The efficiency of memory access
Answer: The number of instructions a CPU can execute in a given time period
What is ‘branch penalty’?
A. The performance loss incurred when the CPU mispredicts a branch instruction
B. A method for optimizing memory access speed
C. A technique for managing CPU performance
D. A process for handling data hazards
Answer: The performance loss incurred when the CPU mispredicts a branch instruction
What is ‘clock cycle’?
A. The time required for the CPU to complete one cycle of its clock signal
B. The process of managing CPU performance
C. A method for increasing memory access speed
D. The duration of a single memory access operation
Answer: The time required for the CPU to complete one cycle of its clock signal
What is ‘cache coherence protocol’?
A. A protocol that ensures consistency of data stored in caches of multiple processors
B. A method for managing memory access
C. A process for optimizing cache performance
D. A technique for handling instruction pipelines
Answer: A protocol that ensures consistency of data stored in caches of multiple processors
What is ‘bus width’?
A. The number of data lines in a bus, determining the amount of data that can be transferred at once
B. The length of the data path in a CPU
C. The size of the memory cache
D. The speed of the memory access
Answer: The number of data lines in a bus, determining the amount of data that can be transferred at once