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What is ‘branch target buffer’ (BTB)?
A. A cache that stores the target addresses of branch instructions to speed up branch prediction
B. A method for managing CPU performance
C. A technique for optimizing data access speed
D. A process for handling instruction pipelines
Answer: A cache that stores the target addresses of branch instructions to speed up branch prediction
What is ‘memory interleaving’?
A. A technique that distributes memory addresses across multiple memory modules to improve access speed
B. A process for managing virtual memory
C. A method for optimizing cache performance
D. A technique for handling data hazards
Answer: A technique that distributes memory addresses across multiple memory modules to improve access speed
What is ‘cache hit’?
A. When the requested data is found in the cache memory
B. When the CPU accesses data from the main memory
C. A technique for managing cache performance
D. A method for optimizing instruction pipelines
Answer: When the requested data is found in the cache memory
What is ‘fetch address’?
A. The memory address from which the next instruction is fetched during the instruction cycle
B. The physical memory address where data is stored
C. The address used for managing cache memory
D. The address generated by the CPU during program execution
Answer: The memory address from which the next instruction is fetched during the instruction cycle
What is ‘data cache’?
A. A small, fast memory located close to the CPU used to store frequently accessed data
B. A technique for managing virtual memory
C. A method for optimizing memory access speed
D. A process for handling data hazards
Answer: A small, fast memory located close to the CPU used to store frequently accessed data
What is ‘load balancing’?
A. The process of distributing workloads evenly across multiple computing resources to optimize performance
B. A technique for managing CPU clock speed
C. A method for increasing memory size
D. A process for handling multi-threaded applications
Answer: The process of distributing workloads evenly across multiple computing resources to optimize performance
What is ‘dynamic scheduling’?
A. A technique that allows instructions to be executed out of order based on availability of execution units and data dependencies
B. A method for managing memory access
C. A process for increasing CPU performance
D. A technique for handling instruction pipelines
Answer: A technique that allows instructions to be executed out of order based on availability of execution units and data dependencies
What is ‘hazard detection’?
A. The process of identifying potential hazards in instruction pipelines to avoid stalls and improve performance
B. A technique for optimizing memory access
C. A method for managing cache memory
D. A process for increasing CPU clock speed
Answer: The process of identifying potential hazards in instruction pipelines to avoid stalls and improve performance
What is ‘register renaming’?
A. A technique that eliminates false dependencies between instructions by using different physical registers for the same logical register
B. A method for managing memory access speed
C. A process for optimizing instruction pipelines
D. A technique for handling cache memory
Answer: A technique that eliminates false dependencies between instructions by using different physical registers for the same logical register